//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef _SER_16X5X_H_
#define _SER_16X5X_H_

#define PC_SERIAL_OUT_BUFSIZE   1024
#define PC_SERIAL_IN_BUFSIZE    2048

#define SERIALPKG_IO_SERIAL_GENERIC_16X5X_FIFO
#define SERIALPKG_IO_SERIAL_GENERIC_16X5X_FIFO_RX_THRESHOLD 4

#ifndef PRI_IO_SERIAL_GENERIC_16X5X_STEP
#define PRI_IO_SERIAL_GENERIC_16X5X_STEP 1
#endif

#define SER_REG(_x_) ((_x_)*PRI_IO_SERIAL_GENERIC_16X5X_STEP)

// Receive control Registers
#define REG_rhr SER_REG(0)    // Receive holding register
#define REG_isr SER_REG(2)    // Interrupt status register
#define REG_lsr SER_REG(5)    // Line status register
#define REG_msr SER_REG(6)    // Modem status register
#define REG_scr SER_REG(7)    // Scratch register

// Transmit control Registers
#define REG_thr SER_REG(0)    // Transmit holding register
#define REG_ier SER_REG(1)    // Interrupt enable register
#define REG_fcr SER_REG(2)    // FIFO control register
#define REG_lcr SER_REG(3)    // Line control register
#define REG_mcr SER_REG(4)    // Modem control register
#define REG_ldl SER_REG(0)    // LSB of baud rate
#define REG_mdl SER_REG(1)    // MSB of baud rate

// Interrupt Enable Register
#define IER_RCV 0x01
#define IER_XMT 0x02
#define IER_LS  0x04
#define IER_MS  0x08

// Line Control Register
#define LCR_WL5 0x00    // Word length
#define LCR_WL6 0x01
#define LCR_WL7 0x02
#define LCR_WL8 0x03
#define LCR_SB1 0x00    // Number of stop bits
#define LCR_SB1_5 0x04  // 1.5 -> only valid with 5 bit words
#define LCR_SB2 0x04
#define LCR_PN  0x00    // Parity mode - none
#define LCR_PE  0x18    // Parity mode - even
#define LCR_PO  0x08    // Parity mode - odd
#define LCR_PM  0x28    // Forced "mark" parity
#define LCR_PS  0x38    // Forced "space" parity
#define LCR_DL  0x80    // Enable baud rate latch

// Line Status Register
#define LSR_RSR 0x01
#define LSR_OE  0x02
#define LSR_PE  0x04
#define LSR_FE  0x08
#define LSR_BI  0x10
#define LSR_THE 0x20
#define LSR_TEMT 0x40
#define LSR_FIE 0x80

// Modem Control Register
#define MCR_DTR  0x01
#define MCR_RTS  0x02
#define MCR_INT  0x08   // Enable interrupts
#define MCR_LOOP 0x10   // Loopback mode

// Interrupt status Register
#define ISR_MS        0x00
#define ISR_nIP       0x01
#define ISR_Tx        0x02
#define ISR_Rx        0x04
#define ISR_LS        0x06
#define ISR_RxTO      0x0C
#define ISR_64BFIFO   0x20
#define ISR_FIFOworks 0x40
#define ISR_FIFOen    0x80

// Modem Status Register
#define MSR_DCTS 0x01
#define MSR_DDSR 0x02
#define MSR_TERI 0x04
#define MSR_DDCD 0x08
#define MSR_CTS  0x10
#define MSR_DSR  0x20
#define MSR_RI   0x40
#define MSR_CD   0x80

// FIFO Control Register
#define FCR_FE   0x01    // FIFO enable
#define FCR_CRF  0x02    // Clear receive FIFO
#define FCR_CTF  0x04    // Clear transmit FIFO
#define FCR_DMA  0x08    // DMA mode select
#define FCR_F64  0x20    // Enable 64 byte fifo (16750+)
#define FCR_RT14 0xC0    // Set Rx trigger at 14
#define FCR_RT8  0x80    // Set Rx trigger at 8
#define FCR_RT4  0x40    // Set Rx trigger at 4
#define FCR_RT1  0x00    // Set Rx trigger at 1

static unsigned char select_word_length[] = {
    LCR_WL5,    // 5 bits / word (char)
    LCR_WL6,
    LCR_WL7,
    LCR_WL8
};

static unsigned char select_stop_bits[] = {
    0,
    LCR_SB1,    // 1 stop bit
    LCR_SB1_5,  // 1.5 stop bit
    LCR_SB2     // 2 stop bits
};

static unsigned char select_parity[] = {
    LCR_PN,     // No parity
    LCR_PE,     // Even parity
    LCR_PO,     // Odd parity
    LCR_PM,     // Mark parity
    LCR_PS,     // Space parity
};

// selec_baud[] must be define by the client

typedef struct pc_serial_info
{
    SERIAL_ADDRWORD base;
    int          int_num;
#ifdef SERIALPKG_IO_SERIAL_GENERIC_16X5X_FIFO
    enum
    {
        sNone = 0,
        s8250,
        s16450,
        s16550,
        s16550a
    } deviceType;
#endif
} pc_serial_info;

#define IO_SERIAL_I386_PC_SERIAL0_IOBASE 0x3F8
#define IO_SERIAL_I386_PC_SERIAL1_IOBASE 0x2F8

#define IO_SERIAL_I386_PC_SERIAL0_IRQ    4
#define IO_SERIAL_I386_PC_SERIAL1_IRQ    3

#define IO_SERIAL_I386_PC_SERIAL0_INT IO_SERIAL_I386_PC_SERIAL0_IRQ + 32
#define IO_SERIAL_I386_PC_SERIAL1_INT IO_SERIAL_I386_PC_SERIAL1_IRQ + 32

//-----------------------------------------------------------------------------
// Baud rate specification, based on raw 24MHz clock

static unsigned short select_baud[] = {
    0,  // Unused
    2304,  // 50
    1536,  // 75
    1047,  // 110
    857,  // 134.5
    768,  // 150
    576,  // 200
    384,  // 300
    192,  // 600
    96,  // 1200
    64,  // 1800
    48,  // 2400
    32,  // 3600
    24,  // 4800
    16,  // 7200
    12,  // 9600
    8,  // 14400
    6,  // 19200
    3,  // 38400
    2,  // 57600
    1,  // 115200
    0,  // 230400
};

#endif /* _SER_16X5X_H_ */
